The present invention relates to a method and apparatus for conducting scan diagnostics on a memory device and in particular to a scan diagnostics shift register for scan-out of an input register, forcing the state of an input register and forcing the state of an output register for a memory integrated circuit.
It has been known to conduct scan diagnostics on, e.g., a combinational logic chip, in conjunction with a scan diagnostics processor programmed to interpret the scan diagnostics output. In a combinational logic chip, scan diagnostics can be implemented by putting a two-stage latch in the logic path, several stages in from an input pin, and connecting these latches serially to form a chain that stretches from the serial input to serial output. The series of latches thus makes up a shift register. With each scan-enabled cycle, data is shifted one position in the register and the logic downstream from the latch will change state to correspond to the new value.
The type of scanning used in connection with combinational logic chips, however, cannot be effectively used in connection with a memory device. This is because in a memory chip, the input information is used to store data in the chip. If the memory chip were allowed to respond to every new bit that passes through the latches, as is done with scanning logic chips, an undesired write could result. It would be useful to obtain scan diagnostics for a memory chip in order to assist in the design and/or maintenance and repair of computer system components.